Non-classical Fault (not stuck-at, stuck-open or stuck-on for CMOS).
Oscillation Fault (or star-faults, bridging faults in combo logic).
Parametric Fault (changes the values of electrical parameters).
Path-delay Fault (*)
Pattern Sensitive Fault
Permanent Fault
Physical Fault
Pin Fault (SA faults on the signal pins of all modules in the circuit).
PLA Fault
Fault Models
Potentially Detectable Fault (a subset of the initialization faults).
IDDQ Fault
Race Fault
Redundant Fault (*)
Segment-delay Fault (*)
Structural Fault
Stuck-at Fault (*)
Stuck-open and Stuck-short Fault (*)
Transistor Fault (Stuck-open and Stuck-short faults)
Transition Fault (*)
Untestable Fault (*)
Logical Faults
Logical faults are used to represent physical faults.
Simplifies the fault analysis process and reduces the # of faults.
A logical fault changes (usually simplifies) the logic function of the circuit.
Structural faults modify the interconnection among the components.
Functional faults change the truth table of a circuit or component.
Most of our discussion is based on the single fault assumption.
However, multiple faults cannot be ignored because:
Some physical faults can generate multiple logical faults.
Testing that does not guarantee 100% fault coverage does not detect some faults and, in certain circuit configurations, these faults can mask faults that are tested.
Fortunately, in most cases, multiple faults are detected by single fault tests.
More on this later.
Single Stuck-at Fault (SSF)
Start with the circuit represented as a netlist of Boolean gates.
Assumes faults only affect the interconnection between gates (structural).
Short and open defects usually cause the signal net or line to remain at a fixed voltage level.
The corresponding logical fault consists of a signal being Stuck-at-0 (SA0) or Stuck-at-1 (SA1).
A circuit with n lines can have 3n - 1 multiple stuck line combinations since each line can be in one of SA0, SA1 and fault-free.
From a practical standpoint, this number is too large.
On the other hand, an n-line circuit can have at most 2n SSF faults.
This number can be further reduced through fault collapsing discussed soon.
SSF Fault Example
How many S
SF
faults can occur on an
n-input
NAND gate?
What fault(s) does the pattern AB = 01 detect?
What is the
minimum
number of tests needed to "detect" all them?
What are the tests?
SSF Fault Example
A
dominant
input value is defined as the value that
determines
the state of the output independent of the other values of the inputs.
What is the dominant input value for the NAND?
How many tests do you need to diagnosis the fault?
Can you distinguish between all of the faults?
SSF Fault Definition
Three properties:
(1) only one line is faulty.
(2) the faulty line is permanently set to either 0 or 1.
(3) the fault can be at an input or output of a gate
.
Fault detection requires:
A test t activates or provokes the fault f.
t propagates the error to an observation point (primary output (PO) or scan latch).
A line whose value changes with f present is said to be sensitized to the fault site.
Fault propagation requires that off-path gate inputs be set to non-dominant values.
Fault Detection
The single stuck fault assumption makes it necessary to distinguish faults on fanout stems from those on fanout branches.
Let Z(t) represent the response of a circuit N under input vector t.
The presence of a fault f transforms the circuit to Nf and its response to Zf(t).
A test vector t detects a fault f iff Zf(t) /= Z(t).
Fault Detection
In this example, any test in which x1 = 0 and x4 = 1 is a test for f.
The expression x1x4 represents 4 tests (0001, 0011, 0101, 0111).
A fault is detectable if there exists a test t that defects f.
If f is undetectable, then no test simultaneously activates f and creates a sensitized path to a PO.
Undetectable faults may appear to be harmless.
However, a complete test set may not be sufficient if one is present.
Fault Detection
The fault b SA0 is no longer detectable by the test t = (1101) if the fault a SA1 is present.
If test t is the only test in the complete test set T that detects b SA0, then T is no longer complete in the presence of a SA1.
Redundancy: A combination circuit that contains an undetectable fault is said to be redundant.
Redundant faults cause ATPG algorithms to exhibit worst-case behavior.
Redundancy
Redundant circuits can be simplified.
Undetectable fault
Simplification rule
AND(NAND) input SA1
Remove input
AND(NAND) input SA0
Remove gate, replace by 0(1)
OR(NOR) input SA0
Remove input
OR(NOR) input SA1
Remove gate, replace by 1(0)
Redundancy is not always undesirable.
Triple modular redundancy (TMR) in fault tolerant design.
Redundancy to avoid hazards
Fault Equivalence and Fault Location
Two faults f and g are considered functionally equivalent iff Zf(x) = Zg(x).
There is no test that can distinguish between f and g. i.e.
, all tests that detect f and g, T
f
and T
g,
are such that:
Functional equivalence partitions the set of all faults into functional equivalence classes, from each of which only one fault needs to be considered.
This property is useful for test generation programs.
Fault equivalence reduces the size of the fault list.
Fault Equivalence and Fault Location
Any n-input gate has 2(n+1) SA faults.
For the NAND gate, the
SA0
on the inputs are equivalent to
SA1
on the output and all three are detected by the same test pattern
AB
=(
11
).
For any n-input gate with n>1, only n+2 single SA faults need to be considered.
Fault equivalence is important for fault location analysis as well.
A complete location test set can diagnose a fault to within a functional equivalence class.
This represents the maximal diagnostic resolution achievable by edge-pin testing.
Note that for large circuits, complete detection or location test sets are generally not used, and therefore, maximum resolution is not achievable.
Equivalence Fault Collapsing
Equivalence fault collapsing is performed in a level-by-level pass from inputs to output using local (gate level) fault equivalences.
Reduction is between 50-60% and is larger, in general, for fanout free circuits.
Equivalence Fault Collapsing
Notice that structural equivalence is confined to fanout free regions.
A SAx stem fault is not functionally equivalent with a SAx fault on any of its branches.
For example, open defects (as shown earlier) can cause faults to show up on only the branch.
However, reconvergent fanout may create structurally equivalent faults in different fanout free regions.
See next example.
Equivalence Fault Collapsing
Our method of equivalence fault collapsing will not identify faults b SA0 and f SA0 as structurally equivalent.
Therefore, the structural equivalence class derived are not maximal.
Faults from this type of structural equivalence and from the general class of functional equivalence are not identified.
The benefit of identifying these additional fault equivalences is not worth the effort, however.
See text for ISCAS'85 benchmark circuit results.
Functional vs. Structural Equivalence
The general process of determining if two arbitrary faults are functionally equivalent is NP-complete.
Functional vs. Structural Equivalence
Our methods determine equivalent faults that are structurally related.
We outlined a process in the context of redundancy earlier (it was applied in the example shown above).
Remove the stuck lines and gates and compare the circuits.
Structural equivalence implies functional equivalence but the converse is NOT true.
Structural equivalence analysis is local, functional is global.
Fault Dominance
If fault detection is the objective (not diagnosis), then fault dominance can be used to further reduce the fault list.
A fault f dominates another fault g if the set of all tests that detect g, T
g
, is a subset of the test set of Tf.
Therefore, any test that detects g
will also detect f.
Since g implies f, it is sufficient to include g in the fault list.
For example, the
SA1
test (g) for input
A
of the NAND gate also detects
SA0
(f) on the output (the same is true for input
B
.)
Therefore,
Z-SA0
can be dropped from the list.
Fault Dominance
It is possible to have to faults f and g such that any test that detects g also detects f, withOUT f dominating g.
The test set Tg consists only of xy = 10.
But f does not dominate g since the faulty circuits are NOT functionally equivalent under Tg.
Although f does not need to be considered, it is difficult to determine this from an analysis of the circuit.
For sequential circuits, it should be noted that equivalence fault-collapsing techniques are valid but dominance fault-collapsing techniques are NOT.
Fault Dominance
For larger input gates.
Dominance fault collapsing is performed from outputs to inputs.
Here, the x indicates the collapsing of the fault via dominance.
We can also, optionally, choose to move the output fault preserved in the equivalence fault collapsing to an arbitrary input.
One such fault list may be: {
A/0
,
A/1
,
B/1
,
C/0
,
C/1
,
D/0
,
E/1
}
Or another may be: {
B/0
,
A/1
,
B/1
,
C/0
,
D/1
,
D/0
,
E/1
}
Checkpoint Faults
Note that these lists contains
only
faults on the PIs.
Any test set that detects all SSFs on the PIs of a fanout free combinational circuit C detects all SSFs in C.
What happens in the presence of fanout?
SAB
= (
010
) detects C SA1,
SAB
= (
001
) detects D SA1 =>
both detect S SA1.
SAB
= (
110
) detects C SA0,
SAB
= (
101
) detects D SA0 => b
oth detect S SA0.
Therefore, SA faults on
stem
dominate SA faults on the fanout branches.
More generally, any test set that detects all SSF on the PIs and fanout branches of C detects all SSF in C.
The PIs and fanout branches are called checkpoints.
Checkpoint Faults
Therefore, it is sufficient to target faults only at the checkpoints.
Structural equivalence and dominance relations can then be used to further collapse the list of faults.
For example, this circuit has 24 SSFs.
But it only has 14 checkpoint faults (the 5 PIs) + g and h.
This leaves 10 faults from the original list of 14 checkpoint faults.
Checkpoint Faults
Example from the text.
A test generation strategy that targets checkpoint faults is valid only for
irredundant
circuits.
In redundant circuits, some checkpoint faults are undetectable.
Test sets that detect all checkpoint faults are not guaranteed to detect all detectable SSFs.
Additional patterns may be required to obtain a complete detection test set.
Fanout and Equivalence and Dominance
Neither equivalence nor dominance relations exist between a stem SAx and an individual fanout branch SAx.
Detection of a stem fault but failure to detect the fanout branch fault.
Fanout and Equivalence and Dominance
Detection of the fanout branch fault but failure to detect the stem fault.
Boolean functions possible.
